Existing Hardware Architectures Research Articles

Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array

Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as inflexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3×, 17.3× improvement in latency, and 54.4×, 17.9× energy savings compared to CPU and GPU.

List-serial pipelined hardware architecture for SCL decoding of polar codes

For polar codes, the performance of successive cancellation list (SCL) decoding is capable of approaching that of maximum likelihood decoding. However, the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously, which are unfriendly to the devices with limited logical resources, such as field programmable gate arrays (FPGAs). In this paper, we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding, where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency. Moreover, we employ only one successive cancellation (SC) decoder core without L×L crossbars, and reduce the number of inputs of the metric sorter from 2L to L + 2. Finally, the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

Base-2 Softmax Function: Suitability for Training and Efficient Hardware Implementation

The softmax function is widely used in deep neural networks (DNNs), its hardware performance plays an important role in the training and inference of DNN accelerators. However, due to the complexity of the traditional softmax, the existing hardware architectures are resource-consuming or have low precision. In order to address the challenges, we study a base-2 softmax function in terms of its suitability for neural network training and efficient hardware implementation. Compared to the classical base- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$e$ </tex-math></inline-formula> softmax function, the base-2 softmax function is a new softmax function that uses 2 as the exponential base instead of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$e$ </tex-math></inline-formula> . From the aspects of mathematical derivation and software simulation, we first demonstrate the feasibility and good accuracy of the base-2 softmax function in the application of neural network training. Then, we use the symmetric-mapping lookup table (SM-LUT) method to design a low-complexity architecture but with high precision to implement it. Under TSMC 28nm CMOS technology, an example design of our architecture has the area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5676 ~\mu m^{2}$ </tex-math></inline-formula> and the power consumption of 13.12 mW for circuit synthesis at the frequency of 3 GHz. Compared with the latest works, our architecture achieves the best performance and efficiency.

G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing

Graph Neural Networks (GNNs) are of great value in numerous applications and promote the development of cognitive intelligence, due to the capability of modeling non-euclidean data structures. However, the inherent irregularity makes GNNs memory-bound, and the hybrid computing paradigm of GNNs poses significant challenges for efficient deployment on existing hardware architectures. Near-Memory Processing (NMP) is a promising solution for alleviating the memory wall problem. In this paper, we present G-NMP, a practical and efficient DIMM-based NMP solution for accelerating GNNs, which accelerates both sparse Aggregation and dense Combination computations on DIMM for the first time. We propose a novel G-NMP hardware architecture to exploit rank-level memory parallelism efficiently, and the G-ISA instructions to reduce host memory requests significantly. We conduct several data flow optimizations on the G-NMP to improve memory-compute overlap and to realize efficient matrix computation. Then we develop an adaptive data allocation strategy for diverse vector sizes to further exploit feature-level parallelism. We also propose a novel memory request scheduling method to achieve flexible and low-overhead DRAM ownership transition between host and G-NMP. Overall, G-NMP achieves consistent performance advantages across diverse GNN models and datasets, and offers 1.46× overall performance and 1.29× energy efficiency on average compared with the state-of-the-art work.

Design, integration and implementation of crypto cores in an SoC environment

PurposeThe paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Inverter startup optimization control for distributed photovoltaic power generation systems

Photovoltaic (PV) power generation is affected by the availability and quality of sunlight. Therefore, PV power generation systems must be frequently started-up when the illumination intensity is not stable. To reduce the number of startup and shut-down events, to prolong the service time of PV inverters, and to reduce the associated impact on the power grid, a novel startup optimization control strategy for distributed PV power generation systems is proposed. The proposed algorithm can implement start–stop inverter control according to different PV power generation conditions without modifying the existing hardware architecture, thus minimizing the startup and shut-down events due to insufficient PV power generation. This protects the key equipment in the PV inverter and enhances the ability of the power grid to adapt to new power generation inputs. The proposed optimization control algorithm is verified experimentally and is found to provide a novel solution for the efficient and reliable control of distributed PV power generation systems. The research presented in this paper is expected to be applicable to numerous engineering projects.

Secure and Efficient Exponentiation Architectures Using Gaussian Normal Basis

Exponentiation in finite fields is an essential operation used in many applications ranging from error control coding to cryptographic computations, while representation in Gaussian normal basis (GNB) offers low complexity arithmetic, especially in hardware architectures. In this article, we propose several new hardware architectures for binary exponentiation in GNB. The proposed architectures make use of different levels of precomputation and the efficient digit-level parallel-in parallel-out, and hybrid-double multipliers. We support our new designs with novel countermeasures against side-channel analysis that require minimal implementation overhead. Moreover, we obtain implementation results for all architectures and provide realistic and fair comparisons with the previously known works available in the literature. It is shown that our newly proposed architectures outperform the existing hardware architectures in terms of area and time complexities and security.

Low Cost Hardware Architecture of Fast Lifting Wavelet Transform for Image Compression

In this work, the researchers have given a low-cost, multiplier-less design with latest DWT (2D lifting technology) for high-speed dual-Z scans. A single dimension parallele row, column processors and five transposing registers are the suggested architecture. Furthermore, a 4N timeline buffer is used to process 2D DWT images with NxN resolution. Flipping architecture is intended to decrease the critical path, replacing multipliers with shifting and adding logic. To reduce transposition and latency buffers, dual Z scanning technology is introduced. The proposed architecture is better for similar performance requirements than the existing hardware architectures. Verilog is defined as the suggested Design Register Transfer Logic (RTL) and is synthesized with Xilinx ISE 14.5. When synthesized with a better hardware efficiency for Xilinx Spartan 6 series field programmable gate array, the suggested architecture works at a frequency of 140.47 MHz.

Grounding thin-air reads with event structures

The key challenge in defining the concurrency semantics of a programming language is how to enable the most efficient compilation to existing hardware architectures, and yet forbid programs from reading thin-air values, i.e., ones that do not appear in the program. At POPL'17, Kang et al. achieved a major breakthrough by introducing the `promising' semantics that came with results showing that it was a good candidate solution to the problem. Unfortunately, however, the promising semantics is rather complicated, and due to its complexity it contains some flaws and limitations that are very hard to address. In response, we present an alternative solution to this problem based on event structures. We show that it is indeed a solution by establishing the standard results about the semantics (DRF theorems, implementation and optimization correctness) as well as a formal connection to the semantics of Kang et al. Further, we show that it is easier to adapt, by extending the semantics to cover features (such as SC accesses) that are not supported by Kang et al. and to rule out some dubious behaviors admitted by the promising semantics.

FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks

Emerging convolutional neural networks (CNNs) tend to be designed with varied per-layer data widths and sparse representations. However, these two features, which bring many redundant computations, have not been exploited simultaneously in existing hardware architectures for CNNs. This paper proposes an energy-quality scalable architecture, namely folded precision-adjustable processor (FPAP), to eliminate all computational redundancies by using folding techniques. On one hand, FPAP decomposes the dominant multiply-accumulate (MAC) operations into multiple adds and folds them into single arithmetic unit. Only effective adds (or part of them) are then calculated serially. Thus, FPAP can adapt to different per-layer data widths and enable precision-adjustable approximate computing. Particularly, FPAP adaptively selects either activation or weight to be decomposed in every single MAC to minimize the total number of adds and clock cycles. On the other hand, a 1-D convolution is undertaken by a multi-tap transposed finite impulse response (FIR) filter, which is folded into one tap to skip MACs with zero weights or activations. Besides, a judicious delay element remapping scheme and a novel genetic algorithm-based kernel reallocation scheme, are developed to reduce the power consumption in a folded FIR filter and mitigate the load imbalance issue caused by irregular sparsity, respectively. With all these optimizations, FPAP is able to reach comparable or even faster processing speed over the corresponding unfolded design in sparse CNNs while consuming smaller area. Experimental results on real CNN models demonstrate that FPAP can scale its energy efficiency from 4.28 to 23.63 TOP/s/W, and area efficiency from 37.79 to 164.15GOP/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively, under the TSMC 28-nm HPC CMOS technology.

A Novel Method of Wireless Data Transfer Through a Variable Focus Lens-Induced Irradiance Modulation of a Gaussian Beam

Mindful of several recent developments in the area of wireless optical data transfer over long and short distances, we present a novel technique to transmit data using an optical carrier. With this technique, the irradiance distribution of a Gaussian optical beam is controlled by passing it through an electronically controlled tunable lens (ECTL). The focal length of the ECTL is controlled by varying the root mean squared voltage of its input electrical drive signal, which alters the irradiance distribution of the Gaussian beam at any fixed plane located after the ECTL. These changes in the irradiance distribution can be interpreted as irradiance modulation with an applied input electrical signal. Variations in the input voltage signal to the ECTL result in variations in the photo-current produced inside a photo-detector of a finite active area. This paper aims to use this unique and simple method for free-space data transfer, and understand the limitations imposed by the currently available commercial ECTL technologies. With rapidly improving ECTL switching speeds and their already widespread use in mobile devices, this method promises an excellent alternative to existing point-to-point wireless data transfer schemes with minimum alterations to the existing hardware architecture of portable mobile devices.

HDL-Based Synthesis System with Debugger for Current-Mode FPAA

The study demonstrates original environment for synthesizing and implementing current-mode analog circuits in the field programmable analog array (FPAA) technology. The described approach is inspired by existing solutions for digital circuits, implemented using a field programmable gate array. The tools are compatible with the existing hardware architecture description standards (VHDL-AMS, HSPICE) and the existing electronic design automation software. The functionality of the system was divided into a synthesis stage (independent on the hardware layer) and an implementation stage (dedicated to an FPAA platform chosen by the user). This article presents parasitics oriented place&route algorithms of the original system and a method for calibrating the analog part. The tools are also equipped with the option of debugging a programmed circuit. The author presents the functionality of the system with an example of an implementation of a 5th order filter pair and a 35–18–26 perceptron with a balanced structure. The summary is an analysis of the complexity of the implemented algorithms and the measurement of program run-times.

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines.

Cascade support vector machines (SVMs) are optimized to efficiently handle problems, where the majority of the data belong to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, SVM classification is a computationally demanding task and existing hardware architectures for SVMs only consider monolithic classifiers. This paper proposes the acceleration of cascade SVMs through a hybrid processing hardware architecture optimized for the cascade SVM classification flow, accompanied by a method to reduce the required hardware resources for its implementation, and a method to improve the classification speed utilizing cascade information to further discard data samples. The proposed SVM cascade architecture is implemented on a Spartan-6 field-programmable gate array (FPGA) platform and evaluated for object detection on 800×600 (Super Video Graphics Array) resolution images. The proposed architecture, boosted by a neural network that processes cascade information, achieves a real-time processing rate of 40 frames/s for the benchmark face detection application. Furthermore, the hardware-reduction method results in the utilization of 25% less FPGA custom-logic resources and 20% peak power reduction compared with a baseline implementation.

FPGA Hardware Acceleration for Visualization with Use of the Ray Tracing Algorithm

This paper deals with the issue of hardware acceleration of photorealistic visualization with use of ray tracing technique in real time. First part of the article briefly introduces ray tracing and presents existing hardware architectures that are accelerating computations with aim to bring real time ray tracing; second part of the article introduces the implementation of the designed solution that represents two modules implemented with use of the VHDL language and the FPGA technology. Modules are accelerating the part of ray tracing algorithm that according to the research requires the most system resources. This part consists of computation needed to find the ray-object intersection. The first module computes ray – sphere intersection, and the second computes ray – triangle intersection. Both modules are composed of number of components, which were optimized and parallel computing was applied in highest possible measure.

VLSI Implementation of an Adaptive Multiuser Detector for Multirate WCDMA Systems

A multirate receiver for WCDMA systems based on the adaptive signature method was designed and implemented. We employed an adaptive signature algorithm to consider two well-known multirate schemes, namely, the low rate and the high rate detector for variable spreading factor systems. In monorate scenarios, numerical experimentations showed that the adaptive signature method outperforms the Rake receiver and reaches the performances of the soft 4-stage multistage parallel interference cancellation receiver. In multirate scenarios, the performance comparison of two multirate schemes in floating-point and fixed-point was analyzed. Reusing the existing hardware architecture previously developed for monorate systems, we targeted the hardware implementation of these two multirate schemes on FPGA components.

Compact hardware liquid state machines on FPGA for real-time speech recognition

Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement real-time, isolated digit speech recognition using a Liquid State Machine. The Liquid State Machine is a recurrent neural network of spiking neurons where only the output layer is trained. First we test two existing hardware architectures which we improve and extend, but that appears to be too fast and thus area consuming for this application. Next, we present a scalable, serialized architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. All architectures support leaky integrate-and-fire membranes with exponential synaptic models. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures have only spanned part of it.

A novel CORDIC-based array architecture for the multidimensional discrete Hartley transform

In this paper, a coordinate rotation digital computer (CORDIC)-based array architecture is presented for computing the multidimensional (M-D) discrete Hartley transform (DHT). Since the kernel of the M-D DHT is inseparable, the M-D DHT problems cannot be computed through the 1-D DHT's directly. Bracewell et al. have presented an algorithm for the M-D DHT through the 1-D DHT's. The existing hardware architectures have been designed using this algorithm. However, the postprocessing required in the algorithm leads to high hardware overhead. This paper presents a new algorithm to compute M-D DHT through a special 1-D transform which is derived through considering both the separable computation and the efficient implementation with CORDIC architectures. This algorithm provides a direct way to compute the M-D DHT separably through 1-D transforms with simpler postprocessing than that in Bracewell's approach. Also, the algorithm exploits the symmetry of the triangular functions to reduce the computational complexity. Using this algorithm, we design an array architecture for the M-D DHT. This architecture features a systolic computing style, PE's with a CORDIC structure, low I/O cost, and the encapsulated new M-D DHT algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Trace-directed program restructuring for AIX executables

This paper presents the design and implementation of trace- directed program restructuring (TDPR) for AIX® executable programs. TDPR is the process of reordering the instructions in an executable program, using an actual execution profile (or instruction address trace) for a selected workload, to improve utilization of the existing hardware architecture. Generally, the application of TDPR results in faster programs, programs that use less real memory, or both. Previous similar work [1–6] regarding profile-guided or feedback-directed program optimization has demonstrated significant improvements for various architectures. TDPR applies these concepts to AIX executable programs at a global level (i.e., independent of procedure or other structural boundaries) running on the POWER, POWER2™, and PowerPC 601™ machines and adds the methodology to preserve correctness and debuggability for reordered executables. Using the prototype tools developed for this effort on a selection of both user-level application prog rams and operating system (kernel) code, improvements in execution time of up to 73% and reduced instruction memory requirements of up to 61% were measured. The techniques used to restructure AIX executables are discussed, and the performance improvements and memory reductions measured for several application programs are presented.